Time interval interpolator

ABSTRACT

A time interval interpolator for producing a series of pulses defining an interval between adjacent input pulses, as in degree points relative to a 90* reference, including a first interpolator producing a first series of pulses referenced to the period of time necessary for a 90* pulse to occur after a fixed time interval, a second interpolator producing a reference count, and a third interpolator providing the desired output from the ratio of the first and second interpolation units. A further embodiment employs two level interpolation employing one 90* period to set up a time base and includes means for preventing more than a fixed number of pulses from being producing in an interval between adjacent input pulses.

United States Patent 1 Blank et a1.

[ TIME INTERVAL INTERPOLATOR [75] Inventors: Hans G. Blank,Brookline; Arthur Margolies, Framingham, both of Mass.

[111 3,745,364 14 1 July 10, 1973 Primary Examiner-John W. Huckert Assistant Examiner-R. E. Hart Attorney-Irving M. Kriegsman [73] Asslgnee: ggfihlgstanboazgzes Incorporated, [57] ABSTRACT A time interval interpolator for producing a series of [22] plied: 1972 pulses defining an interval between adjacent input [21] Appl. M0,; 224,209 pulses, as in degree points relative to a 90 reference, including a first interpolator producing a first series of pulses referenced to the period of time necessary for a [52] US. Cl. 328/41, 328/46 900 pulse to occur after a fixed m6 interval, a Second ll?!- Cl. interpolator p i g a reference count, and a [58] Field Of Search 328/41: 72, 129, interpolator providing the desired Output from the ratio 328/193 340/168 of the first and second interpolation units. A further embodiment employs two level interpolation employ- [56]- References C'ted ing one 90 period to set up a time base and includes UNITED STATES PATENTS means for preventing more than. a fixed number of 3,018,440 l 1962 Cumings 328/41 pulses from being producing in an interval between ad- 3,044,065 7/1962 Barney 328/41 jacent input pulses. 3,538,442 11/1970 Arkell.... 328/41 3,5 4,220 2/1971 Peddie 328/41 15 Chums, 3 Drawing: Flames 905/6/V/7Z SOURCE ez-- Y .34 w 3 b 1 (06K 7 22%; I M r' e90 45 l i 1 DOWN l l CONNIE/i l/P I l 'couA/rm, I

' 1a 1 T b I C Coll/ 62R; W l W t 1 l I (02m, i l 3 l I 94 V Dow/v l cou/vrm TIME INTERVAL INTERPOLATOR BACKGROUND OF THE INVENTION This invention relates to interpolation devices and more specifically to a multistage interpolating device for dividing a time interval into a plurality of subdivisions.

In pulse interval division and like technology, it is desirable to provide a means for accurately defining a time interval between a plurality of pulses in terms of a precise number of interval pulses. The accuracy of such a system lies in providing sufficient numbers of interval pulses to provide accurate definition. The high interval pulse rate systems require correspondingly high frequency clock pulse sources, which, however, in turn often requires more expensive components, particularly in multi-function logic circuitry employing semi-conductor technology.

Such systems find utility in the automotive field, particularly in the automobile ignition systems. In such systems reference or timing pulses are commonly derived at 90 intervals of engine rotation and it is desirable to provide a means wherein the 90 reference seres can be subdivided or defined by means of a series of interval pulses occurring at 1 intervals. The l interval pulses can then be employed in firing the engine at angles other than the 90 reference. The 1 intervals should be provided consistently over a wide range of engine speeds.

In prior automotive systems, the timing phase was provided by the timing between adjacent 90' pulses. Since a wide range of automotive engine speeds, ranging from 600 RPM (revolution per minute) to 6,000 RPM, are not unusual, a variation in timing base of to land more is not unusual. This gives rise to error ratings which can only be compensated in such systems by the use of correspondingly higher clock pulse refer ence sources.

SUMMARY OF THE INVENTION It is therefore a prime object of the present invention to provide a novel and unique interpolation device for dividing a time interval into a predetermined number of subdivisions.

It is a further object of the present invention to provide a novel and unique interpolation device responsive to 90 points in an automotive engine system for dividing the interval between 90 points into 90 subdivisions.

It is another object of the present invention to provide a novel and unique multi-stage interpolation device for dividing a time interval into a predetermined number of subdivisions employing a relatively lower frequency clock pulse source and improving the error rate.

The foregoing objects are accomplished by the use of a multi-stage interpolation technique.

The purpose of the invention is to derive a plurality of desired interval points between a series of reference pulses. To accomplish the foregoing, the invention employs a source of clock pulses and a source of reference pulses. A first interpolator stage is provided, responsive to the clock pulse and reference pulse source, for pro viding a series of output pulses corresponding to a proportion of desired interval points between adjacent reference pulses. An intermediate stage, responsive to the clock source, produces a series of intermediate pulses. A further interpolation stage responds to the ratio of the intermediate stage pulses and the first interpolation stage output to provide the desired output corresponding to the desired interval points.

In a first embodiment, a timer responds to the clock and input signals for providing an output signal defining a timing period beginning at a common or rest position and ending coincidently with the first input signal received by the timing means after the fixed time interval has expired. An interpolator is coupled to the timing means for accumulating clock signals at a rate proportional to the clock signal rate, and is responsive to the timing means output signal for producing a series of output signals proportional to the clock signal rate which corresponds to the number of pulses accumulated by the first interpolator during the timing period. A second interpolator is coupled to the input signals and to the timing means for accumulating input pulses during the timing period, the second interpolator producing a series of output signals proportional to the clock signal rate in response to receipt of the timing means output signal. These output signals correspond to the number of pulses accumulated by the second interpolator during thetiming period. The third interpolater is coupled to the output of the first and second interpolators for accumulating a series of pulses corresponding to the ratio of the output of the first interpolator and the second interpolator. The third interpolator produces a series of output signals proportional to the clock signal rate and corresponding to the maximum count accumulated by the third interpolator, the output signals thus provided thus defining; the interval between adjacent input pulses. The multi-stage interpolation described above permits the use of a lower clock frequency source than would otherwise be employed with a single interpolation stage for producing the desired number of pulses defining the interval between adjacent input pulses.

In a further embodiment, one period between reference signals is employed to set a reference time base for the counter operation. 1

BRIEF DESCRIPTION OF THE DRAWINGS The foregoing brief description of the present invention as well as other objects, advantages and features will become more apparent from the followingdescription and appended drawings wherein:

FIG. 1 illustrates a prior art system of single stage interpolation.

FIG. 2 is a schematic diagram of the present invention employing multi-stage interpolation, and

FIG. 3 is a schematic diagram of a further embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1 a conventional interpolator is illustrated. As shown in FIG. 1 a clock signal source 10 is coupled to a pulse divider 12 which in the example shown is a divide by scaler unit. The clock source 10 for this example is set at a frequency of 900 kHz for reasons which will be explained further below.

The output of the divide by 90 sealer 12 is coupled to an up counter 14 which accumulates the pulses fed thereto. A second input 16 provides a series of pulses representative of the reference signals employed. For the automotive ignition system illustrated, it is conventional to provide a 90 reference signal, or four signals for each engine rotation. The input signals may be provided in conventional manner such as by using a rotating disc with four equally spaced slots connected to rotate with the crank shaft and a magnetic pick-up for sensing the slot positions. The slotted disc can be positioned such as the output pulses may be set at a predetermined spark advance point for use as ignition or firing pulses when a standard spark advance is desired. Other means will be evident to those skilled in the art for providing the engine rotation signals. Such devices include shaft angle encoders, tachometers, or analog to digital converters, all constructed and arranged to function in a known manner.

A series of input signals are fed from the device 16 supplying same to a latching device 18. The latching device performs the function of storing the count accumulated in the counter 14 during the interval between reference pulses. When a reference pulse is received at the input 20 of the latch 18, the count stored in the counter 14 is transferred to and stored in the latch 18 and from there to the down counter 22 which counts down from the accumulated level of the up counter 14 as stored in the latch 18 at the reference signal point at a rate determined by the frequency of the clock source which is coupled to the down counter 22. The up counter 14 is reset for each reference pulse and the latch 18 continually transfers the last accumulated count to the down counter each time the down counter reaches zero. The logic circuitry for accomplishing the reset of the counter and for transfer of a stored count from the latch to the down counter is well known and is not shown.

Clearly, since a dividing scaler is coupled between the up counter 14 and clock signal source 10, and the clock signal source 10 is coupled directly to the down counter 22, the down counter 22 will reach zero many times between adjacent reference input signals.

Each time the down counter 22 reaches zero, an indication is provided by an output pulse from the counter 22 along the line 24. Because the number accumulated by the up counter 14 was generated through a divide by 90 scaler unit 12, the down counter will count to zero at 90 times the rate of the counter 14 and thus 90 zero crossing signals will be obtained from the output 24 of the down counter 22. If the reference signals provided are determined by 90 points of engine rotation, clearly the 90 zero signals provided between adjacent points can be used to provide 1 reference signal points to control engine firing. By way of further illustration, the following example is presented. If the clock source is operative at 900 kHz and the input source rate determined by an engine rotation of 2,400 RPM, the up counter rate will countat a rate determined by the input clock frequency 900 kHz divided by the scaler factor of 90 or at a 10 kHz rate. The 2,400 RPM signal results in 40 revolution per second, or 1 revolution in l/4O of a second, or a quarter of a revolution in l/] 60 ofa second (625 ms). Thus, the input signals provided by the reference 16 which relate to the 90 degree points of engine rotation are provided once every l/l60 of a second (625 ms). In this time period the counter 14 will accumulate a total of 10 kHz/160 or approximately 62 pulses during this interval. Thus, the latch circuit will transfer 62 pulses to the down counter 22 which will count down to zero at a rate determined by the clock source, or 900 kHz in this example. Since the clock source rate is 900 kHz the down counter 22 will take 1/900 of a ms (l.ll us) to count down one pulse or 62/900 ofa ms (62 X 1.11 68 8 #8) to count down from 62 pulses. Since the time period set is l/l60 of a second, the total number of output pulses defined by zero states of the counter 22 will be determined by the number of times the counter 22 counts down from 62 within the time period determined by the space between reference pulses. In this example, the output pulse number is determined by the ratio between the time period of l/ 160 of a second to the count down time period of 62/900 of a ms, 625 ts/688 [1.5, or approximately 90 pulses.

The accuracy required of the l pulses determines the required clock frequency. The source of inaccuracy in the system is due to round off error. Thus, as may be seen in the previous example, for 2,400 RPM the actual count in the up counter 14 should be 62.5. However, the counter will only count 62 during the time frame indicated, and will not reach the count 63 since only half a pulse will have been accumulated. If in the foregoing example the result should have been an accumulated count of 24.99, the round off would have been to 24 as an accumulated count with a resulting 4% error. In longer duration, as toward the end of the reference period, a 4% error can amount to as much as a 3 error in a firing position. Because the round off error will be greatest for the smallest number obtained in the l interpolation at the highest speed, the allowable error at the highest speed determines the clock frequency. For a high RPM rate using the 900 kHz clock, for example at 6,000 RPM, a 4% error is provided. At this speed, 1 results in an accumulated count of 25, for the maximum error of 4%. Slower speeds result in larger counts per degree and correspondingly less round off error.

As seen from the foregoing illustration, a clock source of 900 kHz is needed to provide no greater than a 4% error at 6,000 RPM. In modern solid state technology employing metal oxide semiconductor-large scale integrated circuits and the like it is desirable to use the lowest possible clock frequency. This is particularly true in complex systems where many levels of logic are necessarily performed between clock pulses. By slowing down the clock system, slower speed components may be employed and a less expensive system may be designed. This will be true even where the system becomes more complex and requires additional components because the trade off between speed and numbers of components in an integrated circuit system is weighted far more heavily on the side of cost of components necessary to provide increased speed, rather than on purely a number of components basis.

Referring now to FIG. 2, a preferred embodiment of the basic system in accordance with the invention is illustrated. The principal difference between the present invention and that described in connection with FIG. 1

is that the present invention uses dual interpolation to define the intervals. In addition, it requires a fixed time interval to set up the basic time period value used in the interpolation process whereas the previously described system of FIG. 1 uses the period between pulses. Since the period between 90 pulses varies more than 10 to I over a normal engine speed range, this-time period is not a particularly accurate means of establishing a base level. Accordingly, the present invention employs a multi-stage interpolation structure and illustrates a first interpolator I, designated with the reference numeral 26, a second interpolator I designated with reference numeral 28 and a third interpolator I designated with the reference numeral 30. A first input means 32 provides a series of reference pulses which may correspond to the 90 engine rotation points for an automotive ignition system in the manner as described in connection with the FIG. 1 embodiment above. These 90 points may be derived as described in connection with the FIG. 1 embodiment. A second input means 34 is illustrated as providing a series of clock pulse signals. Referring now to the interpolators, the first interpolator 26 includes a divide by 90 sealer 36 responsive to a series of clock pulse input signals from the input 34 and coupling same to a first up counter 38. The output of the up counter 38 is coupled through a storage latch 40 to a down counter 42. The down counter 42 is coupled'to clock pulse source 34. The second interpolator unit 28 shows an up counter designated as 44 having an input responsive to the series of reference pulses derived from the input 32 thereto and having an output thereof coupled to a storage latch 46 which, in turn, is coupled to the input of a down counter unit 48. The third interpolator unit shows a first up counter 50 having its input responsive to the output of the down counter 48 of the interpolation unit 28. The output of the counter 50 is coupled to the input of a storage latch 52 which, in turn, is coupled to the input of a down counter 54. The output of the down counter 54 appears on line 56 and constitutes the output of the system.

The clock input 34 is connected for synchronization to a timing device 58 which may be any standard form of timer which provides an output after a fixed time delay. The output of the. timing device 58 is coupled to a gating device 60 which also receives an input from the input 32 and has its respective outputs coupled to the latching device 40 of the interpolator 26 and the latching device 46 of the interpolator 28.

Reset signals for each of the up counters arederived from the first 90 pulse appearing along the input after the expiration of the predetermined time period T of the timing device 58. For purposes of clarity, these connections are not shown.

The gating device 60 operates to block passage of a 90 pulse from the input 32 to the latchcircuits for the entire predetermined fixed time interval period of the timing device 58. After the expiration of the fixed timing interval period, the next 90 pulse appearing on the input 32 is passed through the gate 60 to the appropriate latches as shown, defines the rest period, and the cycle beings again. The reset signals can be derived from thegate 60 output. This cycle thus defines the interpolating time base.

As explained in connection with FIG. 1, the latch circuits operate to store the count accumulated in the up counter associated therewith and transfer the stored accumulated count from the up counter to the down counter associated therewith upon receipt of a latch input signal and respond to each zero state of the associated down counter to re-transfer the same previously stored up count to the down counter until the next successive latch input signal transfers a new up count from the up counter to the latch.

Each of the interpolator components functions in the manner described with regard to the interpolator discussed in connection with FIG. 1. That is to say that each of the up counters in each of the interpolators counts up at a rate determined by the rate of the input pulses applied thereto. The latching devices each act upon receipt of an input pulse to store the count accumulated in its associated counter at the point of such receipt and to continue to transfer this stored count to the down counter associated with the latch each time the associated down counter passes through a zero state. Output pulses are derived at the same time. That is, each down counter produces an output pulse each time the down counter reaches zero in a count down.

The fixed time period determining the interpolation time base is determined by the maximum rate change between the appearance of input pulses from the input 32. Where this system is employed in an automobile ignition, this will correspond to acceleration. In such a system since the input signals are received for only each 90 point of rotation, the acceleration error will largely be determined by the period between 90 pulses at the slowest speed for which a calculation is to be performed. Empirically, the relationship as maximum percentage error due to acceleration may be expressed as follows:

where A is acceleration, and R is the rate of revolution in RPM. Thus, for example, at 600 RPM with a 600 RPM per second acceleration, the error would be calculated at 2.5% or 2 in 80. At higher RPM engine speed, the error would decrease rapidly.

A multi-stage interpolator as shown in FIG. 2 is thus designed to employ, as a fixed time base, the time required for the first pulse to appear after a fixed time delay for the slowest speed for all set up times. For the examples shown, the slowest speed cnsidered is 600 RPM, although slower speeds can be handled in the 600 RPM the best performance that can be achieved is an error of 600/40 or 15 RPM in one 90 period since this is the shortest possible set up time.

If 15 RPM is the maximum acceptableerror the set up'time should always be less than 25 ms. Since it is possible to obtain the first 90 pulse just before the end of a timing interval T the total set up time, which is the time to the first 90 pulse after the'end of the period of the set up time 58, could be as long as twice the duration of the time T. A time duration of 12 ms would egnsure that the total set up time will always be less than 24 ms, thus providing the required accuracy.

Referring again to FIG. 2, the operation of the device now becomes apparent. The first interpolator unit 26 will receive pulses proportional to the clock pulse through the scaler 36 in the counter38 for afixed period of time. The up counter 38, instead of terminating at the end of 90 of rotation as in the prior example, is terminated at the 90 pulse which occurs after the time period T of the timing device 58 or in this case after 12 ms. The output of the down counter 42 then appears at intervals which depend on the number of 90 pulses which appeared in the 12 ms time period. Thus, for example, it four 90 pulses appeared within the 12 ms time, the output of the down counter would appear once every 4. A further interpolation unit 30 responds to this output, along with a reference provided by a still further interpolator unit 28 to provide a second level interpolation of the signals appearing at the output of the down counter 42. The second level of interpolation results in a 90 division by providing a series of 90 pulses for each interval between 90 pulses appearing on the input line 32.

By way of example, a specific illustration is shown. It should be noted that the clock frequency for this case is now designed to be 360 kHz or almost one third the rate employed by the single interpolator system of FIG. 1. Thus, at 2,400 RPM, 40 revolutions per second or 160 90 points per second are produced. Each 90 point thus occupies 1/160 of a second or 6% ms. The period of operation set up by the interpolator is that period of time which is required for the first 90 point after the 12 ms period of the timing device 58 to be achieved. Since the present invention requires 6 )4 ms for each 90 point, it is clear that at least two 90 crossings will be achieved in order to reach the first 90 point after 12 ms. The actual period of time transpired from the initial or rest position beginning the operation to the position of the first 90 point after 12 ms is 12.5 ms. The clock frequency in this example of 360 kHz appears along the input line 34 and is divided by 90 by the sealer 36. The resulting 4 kHz counting rate is introduced to the counter 38. Since the timing involved is 12.5 ms, the counter 38 will count the 4 kHz signal in 12.5 ms to achieve a count of 50. The output of the down counter 42 is calculated in the manner described in FIG. 1. This output will be a factor determined by the ratio of the total time period of the system, in this case 12.5 ms, to the number of times the down counter 42 will count down to zero at the clock rate from the count transferred thereto by the up counter 38. The foregoing ratio produces the the following equation:

12.5 ms/[(50/360 kHz) X 2] where 12.5 is the time period, 50 the count in counter 38, 360 kHz the down counter clock rate, and 2 being the number of 90 crossings there are in 12.5 ms. The resultant is an output count of 45 or once per 2. Thus, the counter 42 produces 45 pulses during the time between adjacent input pulses.

Referring now to the interpolator 28, the up counter 44 in the interpolator 28 is directly coupled to the number of input pulses received along the line 32. Thus, in the time frame of the counting mechanism, 12.5 ms, the counter 44 will count to two, representing the number of 90 points in 12.5 ms. The latch 46 is reponsive to the gating device 60 for producing a transfer at the end of each 12.5 ms time frame such that the count transferred from the counter 44, a count of two, will be transferred to the down counter 48. The down counter 48 will count to zero at the clock pulse rate from a count of two, producing an output determined by the following equation:

12.5 rnS/[(2/360kHz) X 2] Again, the factor 2 in the denominator represents the fact that there are two 90 crossings in the 12.5 ms time period. The output pulses received from a down counter 48 thus total 1,125 between adjacent 90 pulses.

A final interpolation unit 30 containing the up counter 50 responds directly to the pulses received from the down counter 48. The transfer time of the third interpolator 30 is dependent upon the rate of output pulses from the down counter 42 of the first interpolator 26. These are conducted to the latch 52 for transfer of the count from the counter 50 to the down counter 54. Thus it will be apparent that between adjacent pulses, the counter 50 will count to a maximum of 1,125. However, the transfer rate determined by the period of energization of the latch 52 will occur once every 45 pulses as determined by the output of the down counter 42. Thus, the maximum state achieved by up counter 50 prior to transference of a count level from the latch 52 to the down counter 54 will be the ratio of the output pulses of the interpolator 28 to the output pulses of the interpolator 26, or 1 /45, or 25. Thus, the count of 25 will be transferred periodically to the down counter 54 which will count to zero at a rate determined by the clock frequency. The number of output pulses appearing along line 56 will be determined by the same relationship employed above:

12.5 mS/[(25/360 kHz) X 2] or a total of 90 pulses appearing between adjacent 90 input signals as they appear along the input line 32. Thus, the interval between adjacent input pulses along line 32 is defined by 90 pulses or an equivalent of 1 pulse per degree. In summary, at 2,400 RPM the speed is 2400/60 RPM or V4 each 90 or /4 revolution requires 1/160 seconds or 6.25 ms. The next 90 pulse after 12 ms timing will be the 2nd. Hence, up counter 44 will contain a count of 2 and the output frequency of counter 48 will be 360/2 kHz kHz. The output frequency of ounter 36 will be 360/90 kl-lz 4 kHz. Time of up count of counter 38 is 90 pulses or 12.5 ms and will thus be 12.5 ms X 4 kHz or 50. An output signal is provided by counter 42 every 50 counts of the clock and an input signal is provided to up counter 50 once every 2 clock pulses. Thus the latch 52 will contain 50/2 or 25 counts. Over the 12.5 ms period of two 90 pulses, the counter 54 will thus provide 12.5 X 360/25 output pulses over two 90 periods, or otherwise equal to one pulse per 1 of rotation.

The following chart represents the operation of the device for varying engine speeds expressed in RPM:

Total Count Count Count Set up Maximum Speed in 48 in 42 in 54 Time Error 600 l 100 100 25 ms 1% 1200 l 50 50 12.5ms 2% 1300 2 92 46 23 ms z 1% 2400 2 50 25 12.5ms 2% 3600 3 50 16" 12.5ms 2% 4800 4 50 12 12.5ms 2% .08%

Round off error With regard to the foregoing it is noted that the round off error in the first interpolator 26 will be between 1 and 2% in every case whereas in the interpolator unit 30 the round off error can be as high as 10% at 6,000 RPM. It should be noted, however, that the interpolator 30 is itself interpolating 1 pulses as a second interpolation operation based upon a first interpolation operation interpolating 10 pulses which are 1% accurate. As a result, the worse case error would be, by way of example, a 1.8" error at the 89 firing position for the 6,000 RPM rate. At 3,000 RPM, the error would be 13 at 89.

To insure greater accuracy, the down counters .of each of the interpolators can be resynchronized on each90input to prevent cumulative error which may take place over several 90 periods. This can be accomplished structurally by employing the input 32 as a source of synchronization signals as well as a source of input signals, as shown by the connection 62. Similarly, the interpolator30 is always resynchronized on every output from down counter 42 to prevent commutation error.

It is therefore seen that by employing the multi-stage interpolation system of the present invention, not only can a better error, rate be achieved, but a lower clock pulse source can be employed without affecting the desired interval subdivisions desired. The present interpolator has been designed to employ a fixed time interval to setup the, counts. It is also possible to construct a two level interpolator in which only'one 90 period is used to set up. the counters. This is illustrated in FIG.

3. As can be seen, the timer 58 and associated logic 60 have been eliminated and interpolator I, has been replaced by fixed divider 49. Additionally, counters 70 and 72, gates 74 and 76, OR gates 80 and 82, and delay elements .84, 86 and 88 have been added. The purpose of elements 70, 72, 74, 76, 80 and 82 is to prevent more than 90 output pulses from being produced when the 90 signal source is decreasing infrequency as in the case of a decelerating engine. Delay elements84, 86 and 88 have been included to prevent race conditions when resetting and reloading counters and latches. Counter 70, set to count to .15, will prevent down counter 42 frombeing decremented by disabling gate 74. In this way, only 6 pulses will appear on signal line 78 until down counter 42 is reloaded by the signal source through OR gate80. Similarly, counter72, set to count to 6, will prevent down counter 54 frombeing decremented by disabling gate 76. In this way, only 6 1 pulses will appear on the output until down counter 54 is reloaded by line 78 throughOR gate 82.

While preferred embodiments of the invention have been shown and described herein,.numerous additions, omissions and changes may be made by those skilled in the art without departing from the spirit and scope of the present invention.

What is claimed is:

l. A time interval interpolator for deriving a plurality of timed interval points between a series of reference pulses comprising a source of clock pulses, a source of said reference pulses, a first interpolator stage responsive to said source of clock pulses and said source of reference pulses for providing a series of output pulses corresponding to a proportion of said desired interval points between a pair of adjacent reference pulses, an intermediate stageresponsive to said source of clock pulses for providing a series of intermediate pulses, and a second interpolator stage responsive to the ratio of said intermediate stage pulses and said first interpolator stage series of output signals for providing a final series of output pulses corresponding to said plurality of desired interval points.

2. The combination of claim 1 wherein said first interpolator stage includes a divider for reducing the rate of application of said clock pulses thereto by a predetermined proportion, and said intermediate stage includes a second divider for reducing the rate of application of said clock pulses by a second proportion, the product of said first and second proportion equalling r the number of desired interval points between adjacent pairs of reference pulses.

3..The combination of claim l wherein each of said .interpolators comprises an up counter, a latch circuit and avdowncounter, said latch circuit responsive-to an .energization thereof to store and transfer-an accumulated count from said up counter to said down counter,

said latch further responsive to each zero state of said down counter to retransfer said accumulated up count to said down counter, said transfer being continued ,.until receipt by said latch of the next successive latch input signal.

-4.,The combination of claim 1 and further including means for, preventing more than a fixed number of pulses from being produced in an interval between adjacent input pulses.

5. T he combination 1 of claim 4 and wherein the means for preventing morethan afixednumber of pulses from being produced in an interval between adjacent input. pulses includes a counter, a gate and an OR gate connected to the first interpolator stage, and a counter, a gateand an OR gate connected to the second, interpolator stage, such that the number of output pulses produced by the first interpolator stage between adjacent input pulses is limited, and the number of output pulses, produced by the second interpolator stage between adjacent pulses produced by the first interpolator stage is limited.

6. A time interval multi-stage interpolator. for derivsiveto saidreference signals for providing an interpolating time base correspondingto the first 90 pulse received after a predetermined fixedtime interval, a first interpolatorrresponsive to a clock source for providing a first series of pulses corresponding to thenumber of 90 reference pulses occurringduring said time 1 base, and a further interpolation device responsiveto said first interpolator and to a further reference pulse source for providing asecond series of pulses corresponding to 1 interval points between said 90 reference signals.

7. The combinationof claim6 wherein each interpolator includes an up counter, a latch circuit and a down counter, said latch circuit responsive to energization thereof to store and transfer an accumulated count from said up counter to said down counter, said latch further responsive to each zero state of said down counter to retransfer said accumulated up count to said down counter, said transfer being continued until receipt by said latch of the next successive latch input signal.

8. The combination of claim 6, wherein said reference pulse source is supplied by a second interpolator responsive to said 90 reference signals.

9. The combination of claim 8, wherein said second interpolator includes an up counter, a latch circuit and a down counter, said latch circuit responsive to energization thereof to store and transfer an accumulated count from said up counter to said down counter, said latch further responsive to each zero state of said down counter to retransfer said accumulated up count to said down counter, said cycle being continued until receipt by said latch of the next successive latch input signal.

10. The combination of claim 9, wherein said first and second interpolator each receive a latchinput signal at the end of each interpolating time base.

11. The combination of claim 10, wherein said third interpolator receives a latch input signal from the output signals of said first interpolator.

12. A time interval multi-stage interpolator for providing a series of output pulses defining an interval between a series of input pulses, comprising first means for supplying said series of input pulses, second means for supplying a clock signal, timing means defining a fixed time interval, means connecting said first and second means to said timing means, said timing means providing an output signal defining an interpolating time base period beginning at a rest position and ending coincidently with the first input signal received by said timing means after said fixed time interval, a first interpolator coupled to said timing means and to said second means for accumulating said clock signals at a rate proportional to said clock signal rate, said first interpolator responsive to said timing means output signal for producing a series of output signals at said clock signal rate corresponding to the number of pulses accumulated by said first interpolator during said timing period, a second interpolator coupled to said first means and said timing means for accumulating said input pulses during said timing period, said second interpolator producing a series of output signals at said clock signal rate in response to receipt of said timing means output signal, said series of output signals corresponding to the number of pulses accumulated by said second interpolator during said timing period, and a third interpolator coupled to the output of said first and second interpolators for accumulating a series of pulses corresponding to the ratio of the output of said first interpolator and said second interpolator, said third interpolator producing a series of output signals at said clock signal rate corresponding to the maximum count accumulated by said third interpolator, said last series of output signals defining an interval between a series of adjacent input pulses.

13. The combination of claim 12, wherein each interpolator includes an up counter, a latch circuit and a down counter, said latch circuit responsive to energization thereof to store and transfer an accumulated count from said up counter to said down counter, said latch further responsive to each zero state of said down counter to retransfer said stored up count to said down counter, said cycle being continued until receipt of the next successive latch input signal by said latch.

14. The combination of claim 13, wherein said first and second interpolator each receive a latch input signal at the end of each interpolating time base.

15. The combination of claim 13, wherein said third interpolator receives a latch input signal from the output signals of said first interpolator.

m. K 2%? UNITED STATES PATENT OFFICE cERTI IcATE 0F CORRECTION Enmm m 337459364 Dated July 1973 It is certified that error appears in the above-identified pecan: and that said Letters Patent awe hereby corrected as shown belowr b in the Abstract, line 13, change "producing" to ---produced-e--.

Dolurnn 1, line 22, change "sauces" to --series--.. y .Column 2, line 7, change "coincidently" to "coincidentally-I, Column 3, line v56, change "revolution" to '--revolutions--. Column 3 line 59, after "90" delete --degree--.

fiolumn '8 line 32, change "ounter" to ----counter--. fiolumn 8 line 63, change "worse" to --worst---. Elaim 12,, lines 9-10, change "coinciently'f to ----'coi.ncidenta11y-.

- Signed and sealed this 20th day, of November 1973 (SEAL) Attest: v

EDWARD M.FLETGHER,JR. RENE D. TEG iT EEYER Attesting Officer I Acting-Commissioner. of Patents 

1. A time interval interpolator for deriving a plurality of timed interval points between a series of reference pulses comprising a source of clock pulses, a source of said reference pulses, a first interpolator stage responsive to said source of clock pulses and said source of reference pulses for providing a series of output pulses corresponding to a proportion of said desired interval points between a pair of adjacent reference pulses, an intermediate stage responsive to said source of clock pulses for providing a series of intermediate pulses, and a second interpolator stage responsive to the ratio of said intermediate stage pulses and said first interpolator stage series of output signals for providing a final series of output pulses corresponding to said plurality of desired interval points.
 2. The combination of claim 1 wherein said first interpolator stage includes a divider for reducing the rate of application of said clock pulses thereto by a predetermined proportion, and said intermediate stage includes a second divider for reducing the rate of application of said clock pulses by a second proportion, the product of said first and second proportion equalling the number of desired interval points between adjacent pairs of reference pulses.
 3. The combination of claim 1 wherein each of said interpolators comprises an up counter, a latch circuit and a down counter, said latch circuit responsive to an energization thereof to store and transfer an accumulated count from said up counter to said down counter, said latch further responsive to each zero state of said down counter to retransfer said accumulated up count to said down counter, said transfer being continued until receipt by said latch of the next successive latch input signal.
 4. The combination of claim 1 and further including means for preventing more than a fixed number of pulses from being produced in an interval between adjacent input pulses.
 5. The combination of claim 4 and wherein the means for preventing more than a fixed number of pulses from being produced in an interval between adjacent input pulses includes a counter, a gate and an OR gate connected to the first interpolator stage, and a counter, a gate and an OR gate connected to the second interpolator stage, such that the number of output pulses produced by the first interpolator stage between adjacent input pulses is limited, and the number of output pulses produced by the second interpolator stage between adjacent pulses produced by the first interpolator stage is limited.
 6. A time interval multi-stage interpolator for deriving 1* interval points between interval reference signals in a rotational system comprising timing means responsive to said reference signals for providing an interpolating time base corresponding to the first 90* pulse received after a predetermined fixed time interval, a first interpOlator responsive to a clock source for providing a first series of pulses corresponding to the number of 90* reference pulses occurring during said time base, and a further interpolation device responsive to said first interpolator and to a further reference pulse source for providing a second series of pulses corresponding to 1* interval points between said 90* reference signals.
 7. The combination of claim 6 wherein each interpolator includes an up counter, a latch circuit and a down counter, said latch circuit responsive to energization thereof to store and transfer an accumulated count from said up counter to said down counter, said latch further responsive to each zero state of said down counter to retransfer said accumulated up count to said down counter, said transfer being continued until receipt by said latch of the next successive latch input signal.
 8. The combination of claim 6, wherein said reference pulse source is supplied by a second interpolator responsive to said 90* reference signals.
 9. The combination of claim 8, wherein said second interpolator includes an up counter, a latch circuit and a down counter, said latch circuit responsive to energization thereof to store and transfer an accumulated count from said up counter to said down counter, said latch further responsive to each zero state of said down counter to retransfer said accumulated up count to said down counter, said cycle being continued until receipt by said latch of the next successive latch input signal.
 10. The combination of claim 9, wherein said first and second interpolator each receive a latch input signal at the end of each interpolating time base.
 11. The combination of claim 10, wherein said third interpolator receives a latch input signal from the output signals of said first interpolator.
 12. A time interval multi-stage interpolator for providing a series of output pulses defining an interval between a series of input pulses, comprising first means for supplying said series of input pulses, second means for supplying a clock signal, timing means defining a fixed time interval, means connecting said first and second means to said timing means, said timing means providing an output signal defining an interpolating time base period beginning at a rest position and ending coincidently with the first input signal received by said timing means after said fixed time interval, a first interpolator coupled to said timing means and to said second means for accumulating said clock signals at a rate proportional to said clock signal rate, said first interpolator responsive to said timing means output signal for producing a series of output signals at said clock signal rate corresponding to the number of pulses accumulated by said first interpolator during said timing period, a second interpolator coupled to said first means and said timing means for accumulating said input pulses during said timing period, said second interpolator producing a series of output signals at said clock signal rate in response to receipt of said timing means output signal, said series of output signals corresponding to the number of pulses accumulated by said second interpolator during said timing period, and a third interpolator coupled to the output of said first and second interpolators for accumulating a series of pulses corresponding to the ratio of the output of said first interpolator and said second interpolator, said third interpolator producing a series of output signals at said clock signal rate corresponding to the maximum count accumulated by said third interpolator, said last series of output signals defining an interval between a series of adjacent input pulses.
 13. The combination of claim 12, wherein each interpolator includes an up counter, a latch circuit and a down counter, said latch circuit responsive to energization thereof to store and transfer an accumulated count from said up counter to said down counter, said latch further rEsponsive to each zero state of said down counter to retransfer said stored up count to said down counter, said cycle being continued until receipt of the next successive latch input signal by said latch.
 14. The combination of claim 13, wherein said first and second interpolator each receive a latch input signal at the end of each interpolating time base.
 15. The combination of claim 13, wherein said third interpolator receives a latch input signal from the output signals of said first interpolator. 